1. Technical Field
The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to an etch used prior to normal etching to modify nested to isolated offsets.
2. Background Art
Ideally, once a particular geometry is chosen for a particular device on a semiconductor wafer, it is desirable that all of these particular devices on the semiconductor wafer be made to the exact same geometry. Deviations in device geometry between particular devices on the same semiconductor wafer may cause one device to run too hot or "leak" carriers or run too slow: the shortest device must meet the leakage specification, while the longest device must meet the speed specification. This means that the design point for speed is determined by the slowest device and the design point for leakage is given by the device having the highest leakage.
Unfortunately, today's semiconductor processing tends to cause deviations in device geometry. This is particularly true for "nested" and "isolated" lines: these lines tend to be different sizes. A nested line is a line of material that is close to one or more other lines of material. An isolated line is a line of material that is not close to any other lines. The difference in size between nested and isolated lines is often called the nested to isolated offset. Nested lines are affected differently than are isolated lines for etching processes used today.
One reason that nested and isolated lines often have different sizes after etching is that there is some amount of lateral etching involved in most types of etching process. This lateral etching tends to affect isolated lines to a different degree than nested lines. For instance, in plasma processing, radio frequency (RF) energy is supplied to a chamber in which semiconductors lie on and are attached to the grounded surface of an electrode. A plasma is generated between this electrode and another electrode. The chemical species in the plasma are determined primarily by the source gas or gases used, although process conditions also affect the types of species in the plasma. In plasma etching, a relatively small DC voltage between the plasma and the wafer/electrode is generated. The various ions, free radicals, and neutrals (non-ionic components) that are generated in the plasma and the neutrals that are pumped into the reactor diffuse to the surface of the electrode and wafer and react with the material being etched to form volatile products that are pumped away. Pure plasma etching tends to be isotropic. This isotropic etching tends to laterally etch isolated lines more because more reactants can diff-use to the sidewalls of isolated lines.
Similarly, Reactive Ion Etching (RIE), also has unwanted lateral etching that affects isolated and nested lines differently. RIE is a type of plasma etching wherein the wafer is placed on the powered electrode and wherein a blocking capacitor is commonly also placed between the electrode and the RF power supply. RIE uses a negative DC voltage developed (by the blocking capacitor) between the plasma and wafer electrode to accelerate ions from the plasma to the wafers. In RIE, some etching occurs by free radicals, but more etching occurs by ions that are accelerated to the surface of the wafer and these ions'interactions with materials on the wafer. Although RIE is a very complex process, RIE is primarily dominated by ion-driven chemical reactions. Part of the ionic etching is by the ions that chemically react at the surface of the wafer and part is by physical removal (sputtering) of material when it is struck by the incoming ion. RIE without sidewall passivation tends to be primarily anisotropic, but will have some isotropic components (assuming no passivation, which will be discussed below). For instance, when using oxygen as a gas in a RIE with an organic material, there is always a thermal, isotropic component that causes lateral etching. In normal RIE, there will be some amount of neutral species that also contribute to isotropic components. These isotropic components can then affect nested and isolated lines differently, leading to nested to isolated offsets. In particular, because isolated lines do not have nearby neighboring lines that shield the isolated line from components that have some lateral velocity, these components (sputtering or reactive) can laterally etch isolated lines to a greater extent. In addition, both nested and isolated lines will be etched at the same time--the isolated lines are etched faster than are the nested lines, but both are etched.
These isotropic effects have been limited somewhat through certain processing steps. For instance, sidewall passivation is one method that has been used to stop the isotropic components (ions and ion-induced reactions) of RIE while allowing the anisotropic components to etch. Passivation is essentially a material added to the plasma that then "plates out" on the surface of the wafer and is designed to resist the chemical reactions occurring at the surface of the wafer. The passivation gets sputtered off the horizontal surfaces of the wafer but attaches and sticks to the vertical surfaces. Some passivation will be sputtered off the sides of lines, but it tends to cover the sides of surfaces very well. Unfortunately, passivation produces a trapezoidal or frustum-shaped device due to shadowing. In addition, passivation tends to plate out more on isolated lines than on nested lines because of shadowing, making these isolated lines larger than the nested lines for the same device. Finally, passivation causes both nested and isolated lines to increase in width.
Another method for limiting lateral etch components is to cool wafers to limit thermal isotropic components. Thus, there are methods of adjusting the plasma materials and materials/methods used on the wafer to allow some adjustment of the RIE to produce varying levels of isotropic and anisotropic etching.
Even so, there is still undesirable isotropic etching during these steps that causes differences in lateral etching between isolated and nested lines. Or, if passivation is being used, there is undesirable growth of the isolated lines without equivalent growth of the nested lines, leading to nested to isolated offsets. In addition, the isolated lines are affected more than the nested lines for both processes. Because of the different effect these processes have on nested and isolated lines, particular devices cannot be made the same size at all locations on the wafer. Thus, there will be a mixture of longer channel, slower devices and shorter channel, faster devices for these particular devices. Some devices may run too hot and leak too much, while other devices run too slow. The entire semiconductor chip, which is made of thousands of devices, then becomes limited by some particular devices that are not the correct, originally planned sizes. Engineers, who are already confronted with choices between speed (shorter devices are faster) and leakage (shorter devices also leak more), are also confronted with designing the nested to isolated offset into chips.
Therefore, without a way to ensure that nested and isolated lines are the same size after processing is complete, chip designers must take into account that there will always be limiting lines on semiconductor chips that determine the power and speed of the chip and that were not originally designed to be limiting.